Hi, Firstly, no complains the Ethernet on my UDOO Quad works perfectly but I have a few questions regarding the pin connections between the RJ45 jack (TRJG16314CNL) and the Micrel ETH PHY (KSZ9031RN). As per the UDOO RevD schematic, the TXRXP_A (TX+) and TXRXM_A (TX-) pins of the PHY have been connected to pins 9 and 10 respectively, which is correct as per the 10 base-T, 100 base-T or 1000 base-T standards. http://pinouts.ru/Net/Ethernet10BaseT_pinout.shtml Similarly, TXRXP_B (RX+) and TXRXM_B (RX-) should be connected to pins 7 and 6 respectively as per the pinout shown in the url above but the these signals have been wired to pins 7 and 8 respectively on the UDOO board. I have also confirmed the correct connection on a reference design provided by Micrel for their ETH PHY (attached with this post). Is there any particular reason this has been done on the UDOO board? Thanks very much. Regards, Shaunak
Remember that this RJ-45 component is not just a simple 8-pin connector, but contains internal magnetics (multiple tiny signal transformers needed for DC isolation) which would otherwise be a separate part on the board. According to the schematic, it also has a connection to +3.3V power, but I'm not sure what that would be used for. Some versions of this part have integrated link-status LEDs also. Anyway, the pin numbering shown is for the solder pads bonding this TRJG* part to the board, which don't necessarily match up with the RJ-45 jack's numbering scheme. In particular, for historical reasons one of the wire pairs on an RJ-45 jack (wired to EIA-568A or 568B standards) straddles another pair, being carried on pins 3 & 6 with the 4/5 pair in between. Though this isn't the best arrangement for signal integrity or trying to maintain constant impedance, we're stuck with it due to the set standard -- but there's no reason the PCB component-side of that split signal shouldn't be placed on adjacent pins for ease of trace routing, etc.
Hi fetcher, Thanks for your response. I do not have the datasheet of the receptacle but from what you say, it must have internal magnetics for protection against surges am I right? However, we are using 100 base T non-crossed network here (using the EIA-568A standard) so I am not able to understand how I am able to get this working on the UDOO board. Unless, there is some re-ordering of pins within the receptacle itself. Is this possible? If the receptacle on the UDOO board had magnetics internally fitted there should have been center tap connections exposed for each differential pair. So a 1000 base T connection you should have 4 center taps. Please correct me if I'm wrong. Thanks very much. Regards, Shaunak
I think the magnetics are necessary for proper impedance-matching to the twisted-pair line as well as for surge protection -- attempting to wire up a jack directly to the PHY chip, even for a quick test usually doesn't work at all. I expect pins are indeed being re-ordered within the jack assembly. If you go to alldatasheet.com and search for "TRJG", although a datasheet isn't available for this exact component , similar ones from the same manufacturer (multi-jack assemblies intended for switches, etc.) do show up, which are probably of similar design. Looking on page 3 of the schematic for those, notice how the pin numbering is consecuive on the board side (P2, P3, P4, P5), but follows Ethernet ordering on the jack side (J1, J2, J3, J6) ... Also, the center-taps are all bonded together to a common pin, and also bypassed to ground using resistors and capacitors within the jack assembly. There's qiute a lot going on inside that component, and it saves a lot of board space over discerete magnetics and filters. I sometimes modify Ethernet devices for passive PoE (accepting or supplying power on the 4,5 and 7,8 pairs that go otherwise unused on 10/100 Ethernet), and one drawback of these jacks including integrated magnetics and bypassing is that they make such hardware hacks more difficult. Of course anything wired for Gigabit, 1000M speeds wouldn't be suitable anyway, with all four pairs being used at that speed. The proper IEEE PoE standard puts DC on top of the data pairs, using center-tap connections on the jack side of transformers, and filters at each end to prevent signal interference, but integrated jacks such as the ones we're talking about, which tie all center-taps together would not be suitable. So, eqiupment desinged for PoE usually has plain jacks and discrete transformers to avoid this problem.
